1. Field of the Invention
This invention relates generally to packages for integrated circuit devices, and placing input and output pads on an integrated circuit device in order to optimize the die size of the integrated circuit device.
2. Related Art
There are various methods for the wire bonding of packages which house integrated circuit (IC) dies. In these methods, the physical limitations in wire bonding have made it difficult to reduce the I/O pad pitch of the IC die below approximately 50-100 microns. In many high density I/O IC designs, this leads to die sizes that are considerably larger than the active core size. An integrated circuit die where the die size is larger than the active core size is referred to as “pad-limited.” Because a pad-limited die contains significant portions of the unused space, the die is larger and fewer dies will be printed per wafer. This means that the die cost is higher.
There are numerous obstacles that limit the number of pads on a die. Various techniques for improving the pad count on a die have been developed, such as staggering the pads. The physical and geometrical structure of the pad itself is a major limiting factor.
These approaches are directed towards the bonding pad configuration of the die. A portion of the conventional single row, in-line bonding pad configuration used for packages is shown in FIG. 1. FIG. 1 illustrates a portion of an IC die 100 having input and output pads 106a-d that provide connections between the IC die 100 and external circuit(s). Each input output pad 106 includes a bond pad 102 that is connected to an IO pad circuit 104. Bond wires 108 are bonded to the bond pads 102 in order to communicate input and output signals to and from the IC die 100. The 10 pad circuits 104 provide any necessary interface circuitry between the IC die 100 and the external circuits connected to the bond pads 108. More specifically, the IO pad circuits 104 provide an interface to the core circuitry of the IC die 100. The core circuitry of the IC die 100 is the primary functioning circuitry of the IC die 100, and varies according the particular IC as will be understood by those skilled in the arts. As such, the IO pad circuits 104 also vary according to the IC die 100, as will be understood by those skilled in the arts. Regarding FIG. 1, it is noticed the IO pad circuits 104 are adjacent to one another and are the same distance d1 from the perimeter 110 of the IC die 100.
FIG. 2 illustrates an IC die 200 with staggered IO pads 208a-d having outer bond pads 202a-c, inner bond pads 204a-b, and IO pad circuits 206a-d. Compared to the conventional single row in-line bonding pad configuration of FIG. 1, the two-row staggered configuration of FIG. 2 provides smaller die size in a pad limited design, or has at least one additional bond pad in the same space. The staggered configuration of FIG. 2 can be implemented in single or multi-tiered package structures. In these package structures, the inner row of bonding pads 204 are bonded to a different surface of the package than the outer row of bonding pads 202, where there is a height differential between the two surfaces. IO pad circuits 206a-d are connected to the respective staggered bond pads 202, 204 using metal traces, for example, metal trace 203. It is again noted that even thou the bond pads 202, 204 are staggered, the IO pad circuits 206 are still adjacent to one another and are equally distant d2 from the perimeter 210 of the IC die 200. The fact that the IO pad circuits 206 are adjacent to one another limits the overall pad density.
There is a need for an approach that increases bonding pad density, which is reliable and cost effective and reduces die size of pad limited designs compared to conventional configurations.